The RTAS 2024 Program Committee nominated 7 papers for an award. The Best Paper Committee evaluated these papers based on the quality of the presentation and the potential scientific and industrial/societal impact. Four papers were recognized as Outstanding Papers and candidates for the Best Paper award, which goes to:

PAAM: A Framework for Coordinated and Priority-Driven Accelerator Management in ROS 2
D. Enright, Y. Xiang, H. Choi, H. Kim
 
In their decision, the Best Paper committee stated that the proposed solution (PAAM), which is presented clearly, successfully addresses the challenge of managing accelerators like GPUs and TPUs in ROS2 applications. Empirical results, supported by the corresponding theoretical analyses, show that PAAM effectively provides predictability when safety-critical applications in ROS2 offload computation to accelerators. The potential short-term impact of the work is high as PAAM is evaluated on a representative setup (software, hardware, and case studies).
Congratulations to the authors of this paper!

The Best Reviewer Committee examined 23 nominated reviews from 17 reviewers using criteria based on inclusiveness, mindfulness, responsibility, and respectfulness. Four reviewers were recognized as Outstanding Reviewers. The selection of the Best Reviewer was conducted by examination of 5 reviews for each Outstanding Reviewer focusing on fairness, i.e., how well each reviewer applied consistent quality to their reviewing workload.

Daniel Casini from Scuola Superiore Sant’Anna in Italy distinguished himself in this category with the most consistent, high-quality reviews that demonstrated fairness to all authors. Congratulations on the Best Reviewer Award Daniel and thank you for your contributions to RTAS 2024.

This is an annual award presented to the recipient at the IEEE Real-Time Systems Symposium. The 2023 recipient of the award is Marco Caccamo. It is a priviledge for RTAS to host the Marco’s award lecture titled “A Long Journey Through Memory Management,  Real-Time Computing, and Multicore Processors”.

Abstract:

Multiprocessor Systems-on-Chip (MPSoC) have been originally designed for high-performance computing applications, but their rich feature set can be exploited to efficiently implement mixed-criticality domains serving both hard real-time tasks, as well as soft real-time tasks. This talk explores SW-based real-time memory management techniques based on pipelining, scheduling, profiling, and an execution model to show how commercially available MPSoCs can support hard real-time and mixed criticality systems, where cores are strictly isolated to avoid contention on shared resources like Last-Level Cache (LLC) and main memory. In cache-based architectures, the use of cache coloring and task profiling were proposed to avoid conflicts in last-level cache. When ScratchPad Memory (SPM) is either available on the hard cores or implementable on the Programmable Logic (PL) of a heterogeneous MPSoC, a multi-phase execution model for real-time tasks has been proposed to avoid conflicts in shared memory. Some working implementations on modern MPSoC platforms are presented, together with results based on sets of benchmark applications.

Biography:

Marco Caccamo studied Computer Engineering at University of Pisa (Italy). Following his degree in computer engineering in July 1997, he earned his Ph.D. in computer engineering from Scuola Superiore Sant’Anna (Italy) in 2002. Shortly after graduation, he joined University of Illinois at Urbana-Champaign as assistant professor in Computer Science and was promoted to associate professor in 2008, then became a full professor in 2014. Since 2018, Prof. Caccamo has been appointed to the chair of Cyber-Physical Systems in Production Engineering at TUM. Caccamo received visiting professorships at ETH Zurich, and TUM Munich as TÜV Süd Stiftung visiting professor and August-Wilhelm Scheer guest professor. He has chaired Real-Time Systems Symposium and Real-Time and Embedded Technology and Applications Symposium, the two IEEE flagship conferences on Real-Time Systems. He also served as General Chair of Cyber Physical Systems Week. He was awarded the NSF CAREER Award. He is a recipient of the Alexander von Humboldt Professorship and he is IEEE Fellow.

* Gabriel Parmer, George Washington University, USA

* Daniel Casini, Scuola Superiore Sant’Anna, Italy

* Christian Dietrich, Technical University Hamburg, Germany

* Silviu Craciunas, TTTech Computertechnik AG, Austria

Congratulations to these esteemed reviewers and thank you very much for your excellent work!

One of these reviewers will be announced as the Best Reviewer at the Award Ceremony at RTAS in Hong Kong. Keep tuned!

Integrating Sporadic Events in Time-triggered Systems via Affine Envelope Approximations
A. Finzi, S. Craciunas, M. Boyer

A Hybrid Approach to WCTT Analysis in a Real-Time Switched Ethernet Network
A. Soni, J. Scharbarg, J. Ermont

PAAM: A Framework for Coordinated and Priority-Driven Accelerator Management in ROS 2
D. Enright, Y. Xiang, H. Choi, H. Kim

Exclusive Hierarchies for Predictable Sharing in Last-level Cache
X. Wang, Z. Wu, R. Pellizzoni, H. Patel

We congratulate the authors of these papers on this achievement! This means these papers are also candidates to become the Best Paper and/or the Best Student Paper. The winner of these awards will be announced during the award ceremony at the conference.

The NSF Student Travel Grants are only open to students who are currently attending US-based Universities/institutions and the SIGBED Student Travel Grants to students that are not primarily attending RTAS.

Information on travel award and how to apply:

https://cps-iot-week2024.ie.cuhk.edu.hk/visa.php#main

Application Deadline: April 5, 2024

This matter has now been resolved and it is possible to book a room at the discounted price. Looking forward to meeting you in person!

https://2024.rtas.org/accepted-papers/

Registration will open soon, so keep tuned!